drm/pancsf: Allow for all GPU interrupts to be shared

Not all platforms have a dedicated interrupt line going into the GIC for each block of the GPU. On Juno FPGAs only have one interrupt line, so the handlers have to share that.

While updating the code make it a bit more consistent in the way the hard and threaded IRQ handlers are structured. This should be in preparation of potentially having only one threaded interrupt handler with custom hooks for each block.

Signed-off-by: Liviu Dudau liviu.dudau@arm.com