Draft: drm/xe: Emit a render cache flush after each rcs/ccs batch
Copy the cache flush from i915, omit PIPE_CONTROL_FLUSH_L3, since it is not clear why it's needed.
Signed-off-by: Thomas Hellström thomas.hellstrom@linux.intel.com
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Copy the cache flush from i915, omit PIPE_CONTROL_FLUSH_L3, since it is not clear why it's needed.
Signed-off-by: Thomas Hellström thomas.hellstrom@linux.intel.com