intel: sync i915_pciids.h with kernel
Align with kernel commits:
0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids") 04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs") 0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID") 605f9c290c1a ("drm/i915: Sort ICL PCI IDs") 514dc424ce4f ("drm/i915: Sort CNL PCI IDs") 32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs") df3478af1d73 ("drm/i915: Sort CML PCI IDs") cd988984cbea ("drm/i915: Sort KBL PCI IDs") b04d36f73771 ("drm/i915: Sort SKL PCI IDs") 9c0b2d30441b ("drm/i915: Sort HSW PCI IDs") 79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers") cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments") 03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs") 812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT") 194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3") 82e84284ab7d ("drm/i915: Update Haswell PCI IDs") 24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids") b50b7991b739 ("drm/i915/dg1: add more PCI ids") d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2") f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs") 0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids") 04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs") 0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID") 605f9c290c1a ("drm/i915: Sort ICL PCI IDs") 514dc424ce4f ("drm/i915: Sort CNL PCI IDs") 32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs") df3478af1d73 ("drm/i915: Sort CML PCI IDs") cd988984cbea ("drm/i915: Sort KBL PCI IDs") b04d36f73771 ("drm/i915: Sort SKL PCI IDs") 9c0b2d30441b ("drm/i915: Sort HSW PCI IDs") 79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers") cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments") 03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs") 812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT") 194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3") 82e84284ab7d ("drm/i915: Update Haswell PCI IDs") 24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids") b50b7991b739 ("drm/i915/dg1: add more PCI ids") d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")
Signed-off-by: Tejas Upadhyay tejaskumarx.surendrakumar.upadhyay@intel.com Reviewed-by: Landwerlin, Lionel G lionel.g.landwerlin@intel.com